Jafarzade, Samira, Jannesari, Abumoslem (2012). A High Dynamic Range Digitally-Controlled Oscillator (DCO) for All-Digital PLL Systems. , 12(2), 16-21.
Samira Jafarzade; Abumoslem Jannesari. "A High Dynamic Range Digitally-Controlled Oscillator (DCO) for All-Digital PLL Systems". , 12, 2, 2012, 16-21.
Jafarzade, Samira, Jannesari, Abumoslem (2012). 'A High Dynamic Range Digitally-Controlled Oscillator (DCO) for All-Digital PLL Systems', , 12(2), pp. 16-21.
Jafarzade, Samira, Jannesari, Abumoslem A High Dynamic Range Digitally-Controlled Oscillator (DCO) for All-Digital PLL Systems. , 2012; 12(2): 16-21.

A High Dynamic Range Digitally-Controlled Oscillator (DCO) for All-Digital PLL Systems

The Modares Journal of Electrical Engineering
Article 3, Volume 12, Issue 2, 2012, Pages 16-21    PDF (195.47 K)
Authors
Samira Jafarzade* 1; Abumoslem Jannesari2
1Tarbiat Modares University, samira.
2Tarbiat Modares University,
Abstract
In this paper, a new high dynamic range Digitally-Controlled Oscillator (DCO) for All-DPLL systems is proposed. The proposed DCO is based on using a ΔΣ modulator as a Digital-to-Analog converter. Using ΔΣ DAC can provide a very high resolution (18-bit) control on the DCO. The ΔΣ DAC output is a 2-level pulse signal that needs to be filtered for cancelling the out of band shaped noise. The used ΔΣ modulator is a 4th order MASH ΔΣ modulator working with the OSR of 128 and the sampling frequency of 450MHz. the proposed DCO is used in a PLL to synthesize the frequency in the range of 1700MHz to 1800MHz for GSM-1800 application. The achieved phase noise for this PLL based synthesizer in whole the range is -115 dBc/Hz at the offset frequency of 500 kHz. The designed ADPLL including the DCO is simulated in ADS with 0.18µm CMOS technology.
Keywords
ADPLL; DCO; ΔΣ DAC; OSR; phase noise
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