SEPYANI, Abdolreza, KABIR, ehsanolah, BEHAZIN, farid (2006). DESIGNING A RECONFIGURABLE ACCELERATOR. , 6(1), 75-84.
Abdolreza SEPYANI; ehsanolah KABIR; farid BEHAZIN. "DESIGNING A RECONFIGURABLE ACCELERATOR". , 6, 1, 2006, 75-84.
SEPYANI, Abdolreza, KABIR, ehsanolah, BEHAZIN, farid (2006). 'DESIGNING A RECONFIGURABLE ACCELERATOR', , 6(1), pp. 75-84.
SEPYANI, Abdolreza, KABIR, ehsanolah, BEHAZIN, farid DESIGNING A RECONFIGURABLE ACCELERATOR. , 2006; 6(1): 75-84.

DESIGNING A RECONFIGURABLE ACCELERATOR

The Modares Journal of Electrical Engineering
Article 6, Volume 6, Issue 1, 2006, Pages 75-84    PDF (1.32 M)
Authors
Abdolreza SEPYANI1; ehsanolah KABIR* 2; farid BEHAZIN3
1YMA research and industrial complex
2TARBIAT MODARES UNIVERSITY
3YAM research and industrial complex
Abstract
Many of the video processing algorithms cannot be implemented in real time on general computers, due to their computational complexity. For an efficient implementation, a custom hardware that can be reconfigured for the algorithm, is used. In this paper a new acceleration hardware based on FPGA elements is proposed. This hardware can be adapted with the processing algorithm through FPGA design reconfiguration. Using a PCI slot, this hardware communicates with a Pc. The FPGAs are programmed through the PCI slot. The video frames are supplied to this hardware for processing. The performance of this hardware is evaluated using warping algorithms. The first and second order warping for a 512*512 frame can be done in 7.9 ms.
Keywords
FPGA; Accelerator; REAL-TIME IMPLEMENTATION; IMAGE WARPING
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